In FIG. 1, it is shown a current sense circuit 10 for a power stage 12 of a single-phase DC-to-DC converter in which a high-side transistor MU and a low-side transistor ML connected between an input voltage VIN and ground GND are switched to thereby generate a channel current IL flowing through an inductor L and a sense resistor RS. In the current sense circuit 10, the two inputs of a transconductive amplifier 102 are connected to the opposite terminals of the sense resistor RS, respectively, so as to detect the channel current IL flowing through the sense resistor RS from which a sense current IS1 is generated, and a sampling-and-holding circuit 104 is connected to the output of the transconductive amplifier 102 to generate a current sense signal IS2 by sampling-and-holding the sense current IS1 under the control of a control clock CLK for the converter 12 to adjust the duty cycles of the drive signals DU and DL for the high-side and low-side transistors MU and ML to modulate the channel current IL. To balance the voltages on the two inputs of the transconductive amplifier 102, a voltage-to-current resistor R1 is inserted between the inverting input of the transconductive amplifier 102 and the sense resistor RS, and the voltage across the voltage-to-current resistor R1 isVR1=VS,  EQ-1where VS is the voltage across the sense resistor RS. The sense current is                                           I            S1                    =                                    V              R1                                      R              1                                      ,                            EQ        ⁢                  -                ⁢        2            and by substituting EQ-1 into EQ-2, it is obtained                               I          S1                =                                            V              S                                      R              1                                .                                    EQ        ⁢                  -                ⁢        3            On the other hand, the voltage across the sense resistor RS isVS=IL ×RS,  EQ-4and from EQ-3 and EQ-4, it is obtained the sense current                                           I            S1                    =                                    I              L                        ×                                          R                S                                            R                1                                                    ,                            EQ        ⁢                  -                ⁢        5            which is proportional to the channel current IL. Therefore, the converter power stage 12 is able to monitor the channel current IL by use of the current sense signal IS2 for the modulation thereof.
A multi-phase converter power stage is constructed with a plurality of single-phase converter power stages connected in parallel. FIG. 2 shows a conventional current sense circuit 20 for a multi-phase DC-to-DC converter power stage having a plurality of channels each including a high-side switch MUi (i=1−N) connected between an input voltage VIN and a phase node, a low-side switch MLi (i=1−N) connected between the phase node and a system reference, and an inductor Li (i=1−N) connected between the phase node and a converter output Vo. To sense the channel currents IL1-ILN of the converter power stage, each channel is provided with a sense resistor RSi (i=1−N) connected between the inductor Li and the converter output Vo, and the two opposite terminals of the sense resistor RSi are connected to the two inputs of a corresponding transconductive amplifier 102, respectively, so as to generate a corresponding sense current IS1i (i=1−N) from the corresponding channel currents ILi for the corresponding sampling-and-holding circuit 104 to further generate the corresponding current sense signals IS2i (i=1−N) to adjust the duty cycles of the drive signals DUi and DLi of the corresponding high-side MOS transistor MUi and the low-side MOS transistor MLi, in order to modulate the channel current ILi (i=1−N).
FIG. 3 shows another conventional art using the same current sense circuit 20 of FIG. 2 for a multi-phase DC-to-DC converter power stage. However, the sense resistors RS1-RSN are inserted between the low-side MOS transistors ML and ground GND, respectively, for each channel, instead of between the converter output Vo and the inductors L1-LN. All the non-inverting inputs of the transconductive amplifiers 102 are grounded, and the inverting inputs thereof are connected to the respective sense resistor RSi (i=1−N) through a respective voltage-to-current resistor Ri (i=1−N). Alternatively, the circuit shown in FIG. 3 can be further modified by replacing the sense resistors RS1-RSN between the low-side MOS transistors ML and ground GND with the ON-resistances of the low-side MOS transistors ML, in which the operational principle thereof is similar to that of the circuit shown in FIG. 2, only that the ON-resistances of the low-side MOS transistors ML are used to serve as the sense resistors for current sensing for each channel of the converter power stage.
When the phases or channels of the converter power stage are increased in number, the pin number and the chip size of the chip containing the current sense circuit 20 both are increased dramatically for multiple transconductive amplifiers 102 are needed. To reduce the pin number of the current sense circuit 20, an improved circuit 30 is proposed as shown in FIG. 4, in which there are still N transconductive amplifiers 102 employed each for one of the channel currents IL1-ILN. However, a common voltage-to-current resistor R1 is connected between the converter output Vo and N switches SW1-SWN to switch one of the transconductive amplifiers 102 to connect to the common voltage-to-current resistor R1, and by turning on the switches SW1-SWN one by one (i.e., each once a time) under the control of control clocks CLK1-CLKN in conjunction with a selected sampling-and-holding circuit 102, the channels are in turn sensed to generate the corresponding current sense signal IS2i. As a result, the current sense circuit 30 is able to reduce N-1 pins for the chip containing the current sense circuit 30. For time-sharing operating this circuit 30, the control clocks CLK1-CLKN shown in FIG. 5 are applied to the switches SW1-SWN and the sampling-and-holding circuits 104. However, due to the large number of the transconductive amplifiers 102, the current sense circuit 30 still requires large chip size.
Moreover, no matter the circuit 20 shown in FIGS. 2 and 3 or the circuit 30 shown in FIG. 4, each channel is provided with a transconductive amplifier 102, it is thus introduced variations of amplifier input offset voltage resulted from variations between different transconductive amplifiers 102 for various channels.
Therefore, it is desired a current sense circuit with reduced pin number and chip size for a multi-phase converter.